Job Description

 We are seeking analog/mixed-signal IP layout and physical design to lead layout implementation, RTL-to-GDSII execution and mentor juniors while working with top EDA tools. Be part of a team building high-performance semiconductor solutions.

Job Description:
• Independently execute layout of analog/mixed-signal IP blocks (e.g., ADCs, LDOs, PLLs, bandgaps, IOs)
• Work closely with logic and circuit designers to meet performance, area, and matching constraints
• Support top-level floorplanning and layout integration
• Perform DRC/LVS/PEX and support sign-off processes
• Participate in technical reviews and contribute to best practices in layout & physical design methodology
• Block execution of physical design, including synthesis, Place and Route and Design and Timing Closure
• Lead and guide junior engineers on the block execution 

Job Requirements

 - Bachelor’s and/or Master’s degree in Computer Science, Computer Engineering, Electronics Engineering or related technical discipline
- At least 6 years of physical design and layout related experience
- Experienced in RTL-to-GDSII flow, floor planning, clock tree synthesis and block-level/chip-level signoff.
- Experienced with physical design/layout EDA tools such as Custom Compiler, Design Compiler, ICCompiler2, Innovus, StarRC, Primetime, ICV, Virtuoso, Calibre.
- Familiar with hierarchical design approach, top-down design, area budgeting, timing budgeting and physical verification convergence
- Knowledge in VLSI layout design especially on high speed data path, high speed memory, TX, RX, DLL, PLL will be an added advantage.
- Strong skills in Make, Python, Perl, TCL, C-shell and other relevant automation scripting tools.
- Willing to travel occasionally. 

Skills