Job Description

Role Overview

As a Senior LSI Physical Design Engineer, you will be responsible for the end-to-end physical implementation of complex, high-performance SoCs. You will drive the execution of the RTL-to-GDSII flow, ensuring that designs meet aggressive power, performance, and area (PPA) targets. The ideal candidate is a power-user of industry-standard EDA tools and possesses a deep understanding of sub-micron process challenges.

Key Responsibilities

• Synthesis & Logic Excellence: Drive logic synthesis and optimization to transform RTL into gate-level netlists, ensuring timing and area constraints are met from the start.
• Full Implementation (P&R): Execute complete Place and Route (P&R) flows, including floorplanning, power grid analysis, clock tree synthesis (CTS), and routing.
• Timing Closure: Lead Static Timing Analysis (STA) and timing sign-off across various corners and modes; perform Signal Integrity (SI) and crosstalk analysis.
• DFT Integration: Implement and verify Design-for-Test (DFT) structures, including scan chains, MBIST, and JTAG, to ensure high test coverage and yield.
• Power Integrity: Conduct comprehensive power analysis (static and dynamic IR drop) and implement low-power design techniques (multi-voltage domains, power gating).
• Physical Verification: Perform sign-off DRC/LVS/ERC/Antenna checks and resolve complex layout issues to ensure 100% tape-out readiness.
• Flow Automation: Develop and maintain scripts (Tcl, Python, or Perl) to improve productivity and enhance the physical design methodology.

Job Requirements

• Education: BS/MS in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 3–10 years of hands-on experience in LSI/ASIC physical design.
• Tool Proficiency: Expert-level experience with at least one major EDA vendor suite:
  Synopsys: Design Compiler, IC Compiler II/Fusion Compiler, PrimeTime.
  Cadence: Genus, Innovus, Tempus.
  Mentor (Siemens): Calibre for physical verification.
• Technical Depth: * Strong understanding of deep sub-micron process nodes (7nm, 5nm, or below).
  Experience with multi-corner multi-mode (MCMM) timing closure.
  Knowledge of UPF/CPF for power-aware implementation.
• Soft Skills: Strong problem-solving abilities, clear technical communication, and the ability to mentor junior engineers (for those at the higher end of the 10-year bracket).

Preferred Qualifications

• Experience with FinFET technology.
• Background in High-Speed SerDes or DDR interface integration.
• Familiarity with Hierarchical Design and Top-level floorplanning.

Skills