Own unit level design and IP integration.

Own design quality check with exposure to various industry standard EDA tool and methodology.

Design timing constraints definition and timing convergence.

Design openbox test planning, assertion check coding and debug.

Design code coverage analysis and closure.

Support silicon power-on and post silicon validation

New design methodology development.

Scripting in flow automation on daily design execution tasks.

Design documentation e.g. micro-architecture and design implementation document.

Good understanding in ASIC/FPGA IP or SoC development cycle.

Knowledge and experience in High-Speed Serial Protocols e.g.: Ethernet, PCIe, MIPI or Universal Transceiver.

Proficient in RTL design with Verilog or System Verilog and design constraints.

Experience in design quality checks methodology e.g.: Lint, CDC, RDC, Fishtail or UPF flow.

Advance user of logic simulation EDA tools e.g.: Cadence Xcelium, Synopsys VCS or Siemens Questa.

Experience in working closely with Design Verification team on testplan, assertions coding, functional and code coverage analysis, tests debug.

Familiarity or experience in Physical Design e.g.: Synthesis, LEC or Timing Closure.

Programming skills (e.g.: Perl, Shell Scripting, TCL, Java, Python or C/C++) and familiar with Linux OS.

Experience in technical writing e.g.: design micro-architecture documentation, paper publication or patent writing.

Self-motivated, strong communication skills, promote innovation and teamwork.

Experience in silicon power-on or hardware validation is a plus.